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发表于 7-7-2008 03:23 AM
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 convention cmos filp flop consists two latches connected back to back. The latch contains 2 inverters connected back2back as memory element. The feedback loop formed by these two inverters able to retain the charge at the latch node. Thats why its also call memory element.
Flipflop have a non-transparent data path behavior thats make it unable to transfer data directly to the output when the passgate is turn on. As i told u flipflop consists of two latches. 1 latch as master and the other as slave. Both latches are in opposite polarity. means when clock high, the master on, and slave turn off. says both latches are high level trigger, data come in at the positive phase and slave latch is on while master latch is off. Therefore the slave latch will receive data and store in the slave memory element. However since master latch is turn off (master and slave latch has opposite polarity), data unable to pass through master latch. So at the negative polarity, master latch is on while slave latch is off. Therefore your data store at slave latch is received by master latch. In this case you will have a falling edge trigger flipflop. See that? Your master latch limit the transparent data flow at the sequential device.For the reset, its because the nand is used as memory element instead of a pure inverter. That make it able to refresh the storing data.
[ 本帖最后由 sunyat99 于 9-7-2008 07:56 AM 编辑 ] |
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