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谁懂VHDL floating point multiplier 里的 exponent adder??
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发表于 19-9-2006 02:22 PM
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是 adder 吗?为什么有underflow overflow?
应该只有carry, 不是吗? |
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发表于 21-9-2006 03:59 PM
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我想你是来自UTM吧??VHDL 很难找人回答的。因为全马只有很少人会。 |
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发表于 21-9-2006 05:26 PM
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不会 VHDL, 但可以试 (白撞):
if(tempe<000000000)then
s:='1';
e:="111111111";
m:="00000000000000000000000";
unflow<='1';
else
if(tempe>111111111)then
e:="111111111";
m:="00000000000000000000000";
ovflow<='1';
end if;
end if;
e_out<=tempe(7 downto 0);
[ 本帖最后由 GeMan 于 21-9-2006 05:28 PM 编辑 ] |
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发表于 21-9-2006 05:46 PM
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但最大的问题是, ea 及 eb 是 signed exponent 还是 unsigned exponent?
signed exponent,比如:
ea=1='00000001'
eb=2='00000010'
e_out=3='00000011' (这个简单)
你是要这样吗?
ea=-1='11111111'
eb=-2='11111110'
e_out=-3='11111101'
unsigned exponent,比如:
ea=1='00000001'
eb=2='00000010'
e_out=3='00000011' (这个简单)
你是要这样吗?
ea=255='11111111'
eb=254='11111110'
e_out=253='11111101'
[ 本帖最后由 GeMan 于 21-9-2006 06:26 PM 编辑 ] |
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发表于 22-9-2006 08:14 AM
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library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity exp_adder is
port(ea,eb:in std_logic_vector(7 downto 0);
e_out: std_logic_vector(7 downto 0);
carry: bit);
end exp_adder;
architecture struct of exp_adder is
begin
process(ea,eb)
variable tempe :std_logic_vector(8 downto 0);
variable e1,e2 :std_logic_vector(8 downto 0);
begin
e1:="0"&ea;
e2:="0"&eb;
tempe:=e1+e2;
e_out=tempe(7 downto 0);
carry=tempe(8);
end process;
end struct;
MMU EE 有学 |
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发表于 13-10-2006 11:16 PM
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KBU都有VHDL啦 |
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发表于 1-11-2006 10:39 AM
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library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity exp_adder is
port(ea,eb:in std_logic_vector(7 downto 0);
e_outut std_logic_vector(7 downto 0);
unflowut bit;
ovflowut bit);
end exp_adder;
architecture struct of exp_adder is
begin
process(ea,eb)
variable tempe:std_logic_vector(8 downto 0);
variable e1,e2:std_logic_vector(8 downto 0);
variable m:std_logic_vector(22 downto 0);
variable e:std_logic_vector(8 downto 0);
variable s:std_logic;
begin
e1:="0"&ea;
e2:="0"&eb;
unflow<='0';
ovflow<='0';
tempe:=e1+e2;
if(tempe<000000000)then
s:='1';
e:="111111111";
m:="00000000000000000000000";
unflow<='1';
else
e_out<=tempe(7 downto 0);
end if;
if(tempe>111111111)then
e:="111111111";
m:="00000000000000000000000";
ovflow<='1';
else
e_out<=tempe(7 downto 0);
unflow<='0';
ovflow<='0';
end if;
end process;
end struct;
试试看,看可以吗?
你没有reset,当然一至set lo... |
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发表于 9-11-2006 02:32 PM
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那里可以买到VHDL software?
你有吗?可以传给我吗? |
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发表于 9-11-2006 05:36 PM
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原帖由 ychenfei 于 9-11-2006 02:32 PM 发表
那里可以买到VHDL software?
你有吗?可以传给我吗?
I already long time not tounch this software liao since four year ago......
i dont know the upgrade version from now.....but i will check for you last wat i have been use
. but can you tell me what kind of thing or project you want to do? like fpga and ect |
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发表于 10-11-2006 11:03 AM
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原帖由 ychenfei 于 9-11-2006 02:32 PM 发表
那里可以买到VHDL software?
你有吗?可以传给我吗?
Altera Quartus II. 去www.altera.com 有得download free web edition.
我这里有很多人用
书本: Fundamentals of Digital Logic with VHDL Design. RM60++ |
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发表于 10-11-2006 11:04 AM
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原帖由 ychenfei 于 9-11-2006 02:32 PM 发表
那里可以买到VHDL software?
你有吗?可以传给我吗?
300MB++ 传到天亮... 寄光碟给你要吗? |
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