flip-flop circuit

心星_pei

为什么flip-flopgate can ats as memory gate?
为什么在转换input的时候
他会retain在之前的setting而不是直接改变output呢？
为什么只有reset之后它才会再回到原来的模式？？

心星_pei

没有人知道？？
为我揭开困扰吧

仙劍

flip flop circuit= NAND gate
NAND gate 是處理logic用的

sunyat99

convention cmos filp flop consists two latches connected back to back. The latch contains 2 inverters connected back2back as memory element.   The feedback loop formed by these two inverters able to retain the charge at the latch node. Thats why its also call memory element.

Flipflop have a non-transparent data path behavior thats make it unable to transfer data directly to the output when the passgate is turn on. As i told u flipflop consists of two latches. 1 latch as master and the other as slave. Both latches are in opposite polarity. means when clock high, the master on, and slave turn off. says both latches are high level trigger, data come in at the positive phase and slave latch is on while master latch is off. Therefore the slave latch will receive data and store in the slave memory element. However since master latch is turn off (master and slave latch has opposite polarity), data unable to pass through master latch. So at the negative polarity, master latch is on while slave latch is off. Therefore your data store at slave latch is received by master latch. In this case you will have a falling edge trigger flipflop. See that? Your master latch limit the transparent data flow at the sequential device.For the reset, its because the nand is used as memory element instead of  a pure  inverter.  That make it able to refresh the storing data.

[ 本帖最后由 sunyat99 于 9-7-2008 07:56 AM 编辑 ]

sunyat99

你很像中四生阿？？ 怎么会对flip flop有兴趣的。。厉害。。

心星_pei

我中五啦
上课有啊~
就说它的application而已
我好奇就来问咯

sunyat99

哇。。中五有学flip flop...好强哦。。哈哈。。。那。。希望我说的。。你会明白。。我也尽量用最浅白的方式来解释了。。。我说的这些都是cmos design...都是非常common 的东东。。。

[ 本帖最后由 sunyat99 于 11-7-2008 11:48 AM 编辑 ]